Parallel array image processors have been used in the past to analyze image data. These array processors generally include a large number of processing modules, one for each pixel in the image. The modules operate substantially simultaneously on the entire image and thus, this type of system is capable of processing image data quite rapidly. However, there are a number of inherent problems with these systems based upon processing element arrays. These include excessive hardware complexity, real-time processing band-width limitations and input/output difficulties.
The shortcomings of parallel array image processors led the Environment Research Institute of Michigan, the assignee of the present invention, to develop an alternative special purpose image processing system. In contrast to the parallel array approach, the image pixels are fed in sequential line scan format to the input of at least one serial neighborhood processing stage. To increase processing time, a plurality of identical stages are connected together in a pipeline. As the pixel data is shifted through the stage, registers are used to sequentially extract a group of neighboring pixels in the image. Neighborhood transformation logic is utilized to perform a pre-programmed transformation of the center pixel based upon the values of the center and its neighbors. Neighborhood transformations are computed at the data transfer clock rate thereby allowing the output of the stage to appear at the same rate as the input. Thus, one pre-programmed transformation is generated for all of the pixels in the image during one pass of the image data through the stage. When a pipeline of stages are utilized, the serial transformed pixel string is coupled to the input of the next stage where another transformation can be carried out.
For further details of such an image processing system the reader is referred to U.S. Pat. No. 4,167,728 entitled "Automatic Image Processor"; U.S. Pat. No. 4,322,716 entitled "Method and Apparatus for Pattern Recognition and Detection", and U.S. Pat. No. 4,398,176 entitled "Image Analyzer With Common Data/Instruction Bus". The above identified patents are hereby incorporated by reference.
The image processing system described above generally employs a host computer which communicates with the special purpose neighborhood transformation stages. The host computer acts as a master controller and operates to perform functions such as programming the stages and transferring the image data between the stages. After the image has been transformed by the transformation stages, the host computer is often used to perform additional analyses on the transformed image. Unfortunately, the transfer of the transformed image from the stages to the host computer takes a considerable amount of time.
In many cellular pattern recognition algorithms, it is often necessary to repeat a transformation of the image until there is no change therein. In other words, it is sometimes necessary to process the image until the pixel values therein no longer are changed in value during one pass through the neighborhood transformation stage. Currently, this is accomplished by using the host computer to perform a pixel by pixel comparison between two images. One image (old) having pixel values that have not been operated on by the stage(s) and the other image (new) having pixel values which have passed through the transformation stage or stages. When the transformation stage has not transformed any of the pixel values in the new image, these two images are identical and therefore it is established that there is no longer any need for passing the image through the stages to undergo any more transformations. Unfortunately, it is computationally expensive and time consuming for the host computer to compare two images for equality since the images typically contain thousands of individual pixels.